The present invention relates to timing design of a semiconductor integrated circuit and, particularly, to timing design applied to 65-nm process technology and 40-nm process technology, for example.
Setup error after performing timing analysis (Static Timing Analysis: STA) has been corrected by resizing a cell such as changing the driving capability of the cell and reducing the threshold voltage (Vt) of the cell. Specifically, data line delay is corrected using an optimizing tool. Then, it is determined from the result of optimization that a path having the setup error remaining after correction of data line delay cannot be modified by automatic optimization using the optimizing tool.
For example, Japanese Unexamined Patent Application Publication No. 2007-257375 discloses a delay analysis device that reduces the burden on a designer and reduces the design period by efficiently and accurately setting the circuit delay of a circuit to be analyzed.
Before 90-nm process technology, it can be determined that clock modification and circuit modification are required when the setup error is not solved by the optimizing tool.
However, as the semiconductor process becomes finer, and in the case where a semiconductor integrated circuit is designed by 65-nm process technology or 40-nm process technology, for example, an issue that data line delay cannot be sufficiently corrected by cell resizing arises. Particularly, such an issue is increasingly common after 40-nm process technology.
Specifically, in the existing timing analysis of a circuit to be analyzed, the setup timing is corrected to a certain degree by layout design, and then the final netlist in which the circuit to be analyzed is expected to satisfy timing constraints is created after that. Layout is then started using the final netlist created in this manner, thereby carrying out timing analysis. In such analysis, although the setup error occurs in about 600 paths in 65-nm process technology, the setup error remains in as many as 15000 paths in 40-nm process technology. Therefore, it has been significantly difficult to check all paths where the setup error has occurred. Further, in most of the remaining errors, a delay value of a cell in a data line is larger than expected. Therefore, the timing of a circuit to be analyzed can be modified by correcting the data line such as upsizing the cell or changing the line path using the optimizing tool.
On the other hand, there are a few paths, among paths where the setup error occurs, that cannot be corrected by the optimizing tool and require manual modification of layout (adjustment of clock delay) and modification of a circuit structure. Further, in timing analysis, the occurrence of errors increases as the analysis proceeds, and it becomes difficult to make sufficient examination of the path to recover the error. Furthermore, when clock modification, circuit modification and the like are made after the analysis proceeds to a certain point, backtracking increases, which makes the modification time-consuming.